JPH0531292B2 - - Google Patents

Info

Publication number
JPH0531292B2
JPH0531292B2 JP19287484A JP19287484A JPH0531292B2 JP H0531292 B2 JPH0531292 B2 JP H0531292B2 JP 19287484 A JP19287484 A JP 19287484A JP 19287484 A JP19287484 A JP 19287484A JP H0531292 B2 JPH0531292 B2 JP H0531292B2
Authority
JP
Japan
Prior art keywords
pattern
resist
contrast
negative
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19287484A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6170718A (ja
Inventor
Yasuhiro Takasu
Yoshihiro Todokoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP19287484A priority Critical patent/JPS6170718A/ja
Publication of JPS6170718A publication Critical patent/JPS6170718A/ja
Publication of JPH0531292B2 publication Critical patent/JPH0531292B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)
JP19287484A 1984-09-14 1984-09-14 パタ−ン形成方法 Granted JPS6170718A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19287484A JPS6170718A (ja) 1984-09-14 1984-09-14 パタ−ン形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19287484A JPS6170718A (ja) 1984-09-14 1984-09-14 パタ−ン形成方法

Publications (2)

Publication Number Publication Date
JPS6170718A JPS6170718A (ja) 1986-04-11
JPH0531292B2 true JPH0531292B2 (en]) 1993-05-12

Family

ID=16298407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19287484A Granted JPS6170718A (ja) 1984-09-14 1984-09-14 パタ−ン形成方法

Country Status (1)

Country Link
JP (1) JPS6170718A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100278987B1 (ko) * 1998-02-18 2001-02-01 김영환 반도체장치의제조방법

Also Published As

Publication number Publication date
JPS6170718A (ja) 1986-04-11

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